1. Field of the Invention
The present invention relates to a structure of a data output buffer of a semiconductor integrated circuit device.
2. Description of the Background Art
A phenomenon called electrostatic discharge (represented as ESD hereinafter) is seen when a semiconductor device is brought into contact with a material that is discharged electrostatically via a package lead. This discharge phenomenon can cause a high voltage to be applied inside the device to induce breakdown therein.
Various models such as a human body model (referred to as HBM hereinafter), a machine model (referred to as MM hereinafter) and a charged device model (referred to as CDM hereinafter) can be considered with respect to the ESD breakdown. ESD testing according to such models is implemented as one type of reliability testing of a semiconductor device.
A HBM is a model of breakdown generated at the time of electrostatic discharge as a result of a human being with static electricity forming contact with a device. A MM is a model of breakdown generated at the time of electrostatic discharge induced by a metal accumulated with static electricity forming contact with a device. Both models are tested according to the capacitor discharge method shown in the schematic diagram of FIG. 12.
According to the capacitor discharge method, a discharge capacitor CD is connected to a power supply V via a switch SW and a power supply protection resistor RV. As a result, predetermined charge is stored in discharge capacitor CD. At time t1, switch SW is effected to apply a test voltage across the power source pin and the measurement pin of a device DUT via a discharge resistor RD.
The resistance of a device of interest DUT is tested by applying a high voltage.
The applied voltage, the discharged resistance and the like differ in the HBM and MM.
The ESD test was carried out conventionally by the above capacitor discharge method. However, there are some devices that result in ESD breakdown even when the resistance is sufficient in the HBM test and MM test. Therefore, the CDM test is additionally included these few years.
In a CDM test, the breakdown is modeled that occurs at the time of electrostatic discharge when the package lead of a device is charged by friction and the like to cause electrostatic discharge through the terminal of the device.
FIG. 13 is a schematic diagram showing a structure of a tester of the charged device method.
This structure is an example of implementation of the CDM test. Initially, switch SW1 conducts, and the electrode plate where the under-testing device DUT is placed is discharged.
When measurement is carried out, switch SW1 is turned off, and switch SW2 is turned on. Accordingly, power supply voltage V is applied to the electrode plate, and a potential substantially equal to voltage V is applied to the chip and the package lead via the parasitic capacitance Cpkg present between the electrode plate and the semiconductor chip in the under-testing device.
At time t1, a discharge rod is connected to a pin to be measured (a package lead), whereby the potential of the package lead rapidly falls to the level of the ground potential. Device DUT is tested by this sudden discharge.
In a semiconductor device, the internal circuit connected to an external device via the package lead is mainly divided into two types.
The first is the input buffer circuit receiving a signal from an internal pin. The second is the output buffer for transmitting a signal to the internal pin.
FIG. 14 is a circuit diagram showing an example of an input protection circuit inserted between an input buffer circuit and an input pad for the purpose of accommodating ESD breakdown.
In the input buffer circuit of a MOS integrated circuit, an input signal is generally sensed via the gate of a transistor. When a high voltage is directly applied to the gate oxide film, breakdown of the oxide film occurs. The breakdown electric field of a gate oxide film SiO.sub.2 is approximately 7.times.10.sup.6 V/cm. Therefore, a transistor having a gate oxide film of 10 nm in thickness will be broken down when a voltage of approximately 7 V is applied to the gate thereof.
The input protection circuit of FIG. 14 is inserted to prevent this breakdown. Particularly, a transistor TR1 is called a "field transistor", which serves to prevent ESD breakdown.
A resistor R1 connected between the input pad and the drain of field transistor Tr1 has a resistance of, for example, several ohms. Resistor R1 is formed of an interconnection layer such as of polysilicon.
A resistor R2 having a resistance of 100-200.OMEGA. and formed of a diffusion layer and the like is inserted between the drain of field transistor Tr1 and the drain of field transistor Tr2.
By this insertion of a relatively great resistor R2, discharge towards the ground potential is effected by transistor Tr1 before the high voltage from the input pad is transmitted to the internal circuit.
Transistor Tr2 has its drain connected to one end of transistor R2 at the input buffer side and has its source connected to the ground potential. Transistor Tr2 has its gate and source connected. Therefore, transistor Tr2 is diode-connected.
Transistor Tr2 functions to clamp the level of the potential transmitted from the input pad.
FIG. 15 is a sectional view of a field transistor.
In a field transistor, a source S formed of a diffusion layer is isolated from a drain D by an oxide film as in general element isolation. More specifically, the field transistor has a structure in which the gate oxide film is equal in thickness to the oxide film used for element isolation.
When a high voltage is applied from the input towards the drain of the field transistor, the charge will flow towards the ground potential via two paths set forth in the following.
One path is indicated by PA in FIG. 15. The field transistor attains a punch through state, so that charge flows from the drain to the source.
The other path is indicated by PB in FIG. 15. The PN junction between the drain of the field transistor and the substrate exhibits avalanche breakdown, whereby the charge flows towards the substrate. By this charge flow through the current path, the high voltage applied towards the input pad is absorbed.
Here, resistor R2 functions to prevent the electrostatic charge from arriving at the inner circuit before the charge absorption by the field transistor.
By insertion of such elements, ESD breakdown can be reliably suppressed in an input buffer circuit.
FIG. 16 is a circuit diagram showing a structure of a conventional output buffer circuit.
In FIG. 16, a resistor Rout is inserted to compensate for ringing in the output, and has a resistance of approximately several ohms.
An output buffer circuit 2000 includes transistors Q1 and Q2 connected in series between power supply potential Vcc and ground potential GND. Transistor Q1 receives a signal for an H data output at its gate. Transistor Q2 receives a signal for an L data output at its gate. Resistor Rout is connected between the node of transistors Q1 and Q2 and the output pad.
FIG. 17 is a plan view showing a layout of the conventional output buffer circuit 2000 of FIG. 16.
An H data output signal or an L data output signal is transmitted to respective gates of the drive transistor of the output buffer by a first metal interconnection (represented as "1AL" hereinafter) 70.
It is assumed that the first metal interconnection 1AL represents an aluminum interconnection of, for example, the first layer.
A first metal interconnection 71 connects each drain of the drive transistor of the output buffer. A second metal interconnection (represented as "2AL" hereinafter) 72 forms an output pad.
A second interconnection 73 is the power supply interconnection for supplying power supply potential Vcc or GND to a drive transistor.
Here, it is assumed that second metal interconnection 2AL is the aluminum interconnection of, for example, the second layer.
A polysilicon electrode 74 that is the gate electrode of the drive transistor is connected to first metal interconnection 70 via a through hole 76.
First and second metal interconnections 1AL and 2AL are connected via a through hole 75.
The gate electrode, the diffusion layer, the polysilicon resistor and the like are connected to first metal interconnection 1AL via contact hole 76.
A polysilicon resistor 77 corresponds to resistor Rout of FIG. 16.
In output buffer circuit 2000, a portion of the signal generated in the device must be provided to an external device. Therefore, arrangement must be provided so that a great current drive capability of the drive transistor is acquired. It is therefore not possible to use an input protection circuit including a resistor component as in the input buffer circuit.
More specifically, a current of approximately 100 mA, for example, is required to be supplied to the output pad with a power supply voltage of, for example, 3 V.
It is therefore difficult to set a resistor Rout of 100 .OMEGA., for example, in principle.
However, the drive transistor of the output buffer circuit will be greater in size than the other transistors in the device, in other words, has a greater gate width, since the aforementioned current drivability is required. Thus it is therefore possible in principle to absorb the charge efficiently when a high voltage is applied via the PN junction between the source drain and the substrate of the MOS transistor.
However, as mentioned above, there are devices that exhibit ESD breakdown in an output buffer circuit in practice even when the resistance is sufficient in the HBM and MM tests.